If you believe that … you’ll believe anything *cough*
The first Intel Tiger Lake processors to ship with Gen12 graphics (Xe) are scheduled to arrive in 2020/2021, and we’re now hearing a bit more about the architecture that will be underpinning them. Last week, Intel released a new set of Linux patches that describe a new Display State Buffer (DSB) engine, which is said to handle batch submit display register programming.
According to the documentation provided with the patch, DSB is described as “[reducing] loading time and CPU activity, thereby making the context switch faster. DSB Support added from Gen12 Intel graphics based platform.” In other words, the CPU is going to be tasked less, leaving its precious resources available for other operations.
Intel has also referenced Gen12 and architecture in a new merge request in GitHub. The shift to Gen12 is described by Intel as providing “the most in-depth” EU ISA remake since the i965 debuted over a decade ago.
Read more at Hothardware