Intel Unleashes 56-core Xeon “Cascade Lake” Processor to Counter AMD’s 64-core EPYC

And you thought Intel was going to idly stand by and let AMD take all the lime-light?

Intel late Tuesday made a boat-load of enterprise-relevant product announcements, including the all important update to its Xeon Scalable enterprise processor product-stack, with the addition of the new 56-core Xeon Scalable “Cascade Lake” processor. This chip is believed to be Intel’s first response to the upcoming AMD 7 nm EPYC “Rome” processor with 64 cores and a monolithic memory interface. The 56-core “Cascade Lake” is a multi-chip module (MCM) of two 28-core dies, each with a 6-channel DDR4 memory interface, totaling 12-channel for the package. Each of the two 28-core dies are built on the existing 14 nm++ silicon fabrication process, and the IPC of each of the 56 cores are largely unchanged since “Skylake.” Intel however, has added several HPC and AI-relevant instruction-sets. 

To begin with, Intel introduced DL Boost, which could be a fixed-function hardware matrix multiplier that accelerates building and training of AI deep-learning neural networks. Next up, are hardware mitigation against several speculative execution CPU security vulnerabilities that haunted the computing world since early-2018, including certain variants of “Spectre” and “Meltdown.” A hardware fix presents lesser performance impact compared to a software fix in the form of a firmware patch. Intel has added support for Optane Persistent Memory, which is the company’s grand vision for what succeeds volatile primary memory such as DRAM. Currently slower than DRAM but faster than SSDs, Optane Persistent Memory is non-volatile, and its contents can be made to survive power-outages. This allows sysadmins to power-down entire servers to scale down with workloads, without worrying about long wait times to restore uptime when waking up those servers. Among the CPU instruction-sets added include AVX-512 and AES-NI.

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Source: HotHardware via TPU

 

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