DDR5 is the fifth generation of Double Data Rate Synchronous Dynamic Random Access Memory, aka DDR5 SDRAM. Its development was initiated in 2017 by the industry standards body JEDEC (Joint Electron Device Engineering Council) with input from the leading global memory semiconductor and chipset architecture vendors, including Kingston. DDR5 is designed with new features for higher performance, lower power, and more robust data integrity for the next decade of computing. DDR5 debuted in 2021.
Greater starting speed performance
DDR5 debuts at 4800MHz, while DDR4 tops out at 3200MHz. This represents a 50% increase in bandwidth. In cadence with compute platform releases, DDR5 has planned performance increases that will scale to 6400MHz.
Reduced power / increased efficiency
At 1.1V, DDR5 consumes ~20% less power than DDR4 equivalent components at 1.2V. In addition to conserving battery life in laptops, it also has a significant advantage for enterprise servers working around the clock.
DDR5 modules feature onboard Power Management Integrated Circuits (PMIC), which help regulate the power required by the various components of the memory module (DRAM, register, SPD hub, etc). For server-class modules, the PMIC uses 12V; for PC-class modules, it uses 5V. This makes for better power distribution compared to previous generations, improves signal integrity, and reduces noise.
DDR5 utilizes a new device that integrates the Serial Presence Detect (SPD) EEPROM with additional hub features, manages access to the external controller, and decouples the memory load on the internal bus from the external.
Dual 32-bit subchannels
DDR5 splits the memory module into two independent 32-bit addressable subchannels to increase efficiency and lower the latencies of data accesses for the memory controller. The data width of the DDR5 module is still 64-bit. However, breaking it down into two 32-bit addressable channels increases overall performance. For server-class memory (RDIMMs), 8-bits are added to each subchannel for ECC support for a total of 40-bits per subchannel, or 80-bits per rank. Dual rank modules feature four 32-bit subchannels.
The notch in the center of the module acts like a key, aligning with DDR5 sockets to prevent DDR4, DDR3, or other unsupported module types from being installed. Unlike DDR4, DDR5 module keys differ between module types: UDIMM and RDIMM
On-die ECC (Error Correction Code) is a new feature designed to correct bit errors within the DRAM chip. As DRAM chips increase in density through shrinking wafer lithography, the potential for data leakage increases. On-die ECC mitigates this risk by correcting errors within the chip, increasing reliability, and reducing defect rates. This technology cannot correct errors outside of the chip or those that occur on the bus between the module and memory controller housed within the CPU. ECC-enabled processors for servers and workstations feature coding that can correct single or multi-bit errors on the fly. Extra DRAM bits must be available to allow this correction to occur, as featured on ECC-class module types such as ECC unbuffered, registered, and load reduced.
Additional temperature sensors
Server-class DDR5 RDIMMs and LRDIMMs add temperature sensors to the ends of the modules to monitor thermal conditions across the length of the DIMM. This allows for more precise control of system cooling, as opposed to the throttling of performance seen in DDR4 for high temperatures.