Interesting news … could we see an imminent new chipset for this high-end desktop (HEDT) market?
Taken from TPU … Enthused with its IPC leadership, Intel is possibly planning a return to the high-end desktop (HEDT) market segment, with the “Alder Lake-X” line of processors, according to a Tom’s Hardware report citing a curious-looking addition to an AIDA64 beta change-log. The exact nature of “Alder Lake-X” (ADL-X) still remains a mystery—one theory holds that ADL-X could be a consumer variant of the “Sapphire Rapids” microarchitecture, much like how the 10th Gen Core “Cascade Lake-X” was to “Cascade Lake,” a server processor microarchitecture. Given that Intel is calling it “Alder Lake-X” and not “Sapphire Rapids-X,” it could even be a whole new client-specific silicon. What’s the difference between the two? It’s all in the cores.
While both “Alder Lake” and “Sapphire Rapids” come with “Golden Cove” performance cores (P-cores), they use variants of it. Alder Lake has the client-specific variant with 1.25 MB L2 cache, a lighter client-relevant ISA, and other optimizations that enable it to run at higher clock speeds. Sapphire Rapids, on the other hand, will use a server-specific variant of “Golden Cove” that’s optimized for the Mesh interconnect, has 2 MB of L2 cache, a server/HPC-relevant ISA, and a propensity to run at lower clock speeds, to support the silicon’s overall TDP and high CPU core-count.
Intel probably learned from “Skylake-X” and “Cascade Lake-X” that an HEDT processor should match or exceed the mainstream-desktop part at everything (including gaming), so its buyers don’t feel like performance of IPC-sensitive/less-parallelized workloads is being traded in for brute multi-threaded performance. ADL-X could hence even be a whole new silicon+package combination, with “Golden Cove” client cores, perhaps some “Gracemont” E-core clusters, and characteristic-HEDT features, such as more memory channels and more PCIe lanes; but most importantly, the ability for the processor to run some of its P-cores at very high clock-speeds.
Source: TPU
