As it’s getting more difficult to cram transistors next to each other in chips, and we near the end of Moore’s Law, the only choice is to go vertical. Literally. That’s the essence of 3D chip design, and it’s the crux of a major Intel announcement this morning: It’s developed the first 3D chip architecture that allows logic chips — things like the CPU and graphics — to be stacked together. This isn’t just a far-flung research project, either. Intel claims we’ll see the first products to use Foverus in the second half of next year.
We’ve seen 3D-stacked high bandwidth memory in video cards like AMD’s R9 Fury X (which was designed by former AMD graphics head Raja Koduri, who’s now spearheading Intel’s core and visual computing group), but Foveros takes the concept to a whole new level. Intel says it’ll allow for smaller “chiplets,” which describes fast logic chips sitting atop a base die that handles things like power, I/O and power delivery. The debut Foveros product sounds intriguing: it’ll be a 10 nanometer compute element (something Intel has had a lot of trouble building) on a base die that’s typically used in low-power devices.
The big takeaway is that Intel will be able to cram more power and better efficiency into chip designs that take up less space. The company wouldn’t say where, exactly, the first Foveros-equipped chip will end up, but it sounds like it’ll be ideal for incredibly thin and light machines. Perhaps Qualcomm’s new PC Snapdragon processor, which is aimed for always connected laptops, could actually have some competition from Intel.